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56f8300 16-bit digital signal controllers freescale.com 56f8323 evaluation module user manual MC56F8323EVMum rev. 2 07/2005
document revision history version history description of change rev 1.0 initial public release rev 2.0 updated look and feel
table of contents table of contents, rev. 2 freescale semiconductor i preliminary preface preface-vii chapter 1 introduction 1.1 56f8323evm architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 56f8323evm configuration jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 56f8323evm connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 chapter 2 technical summary 2.1 56f8323. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 rs-232 serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3 debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.3.1 jtag connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.3.2 parallel jtag interface connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.4 external interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.7 daughter card connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.7.1 peripheral daughter card expansion connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.7.2 memory daughter card expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.8 serial 10-bit 4-channel d/a converter (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.9 motor control pwm signals and leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.10 can interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.11 software feature jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.12 peripheral expansion connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.12.1 pwm port a expansion connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.12.2 serial peripheral interface #0 ex pansion connector. . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.12.3 serial peripheral interface #1 ex pansion connector. . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.12.4 serial communications port #0 expansion connector . . . . . . . . . . . . . . . . . . . . . . 2-25 2.12.5 serial communications port #1 expansion connector . . . . . . . . . . . . . . . . . . . . . . 2-25 2.12.6 encoder #0 / quad timer channel a expansion connector. . . . . . . . . . . . . . . . . . 2-26 2.12.7 timer channel c expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.12.8 flexcan expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.12.9 a/d port a expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
MC56F8323EVM user manual, rev. 2 ii freescale semiconductor preliminary 2.12.10 gpio port a expansion co nnector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.12.11 gpio port b expansion co nnector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.12.12 gpio port c expansion co nnector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.12.13 irqa / reset / clock expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.13 test points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 appendix a 56f8323evm schematics appendix b 56f8323evm bill of material
list of figures list of figures, rev. 2 freescale semiconductor iii preliminary 1-1 block diagram of the 56f8323evm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2 56f8323evm jumper reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-3 connecting the 56f8323evm cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 2-1 schematic diagram of the rs-232 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-2 schematic diagram of the clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-3 schematic diagram of the debug led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-4 block diagram of the parallel jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2-5 schematic diagram of the user interrupt interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-6 schematic diagram of the reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-7 schematic diagram of the power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-8 serial 10-bit, 4-channel d/a converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2-9 pwm interface and leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2-10 can interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 1 2-11 software feature jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2-12 typical analog input rc filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
MC56F8323EVM user manual, rev. 2 iv freescale semiconductor preliminary
list of tables list of tables, rev. 2 freescale semiconductor v preliminary 1-1 56f8323evm default jumper options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 2-1 flow control header options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-2 sci1 jumper options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-3 rs-232 serial connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-4 led control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-5 jtag connector description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-6 parallel jtag interface disable jumper selection . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-7 parallel jtag interface connector description . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2-8 parallel jtag interface voltage selection jumper . . . . . . . . . . . . . . . . . . . . . . 2-10 2-9 peripheral daughter card connector description . . . . . . . . . . . . . . . . . . . . . . . 2-14 2-10 memory daughter card connector description . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2-11 d/a header description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2-12 can signal isolation jumper options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2-13 can header description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2-14 pwm port a connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2-15 spi #0 connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2-16 spi #1 connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2-17 sci #0 connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2-18 sci #1 connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2-19 timer a signal connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2-20 timer channel c connector description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2-21 can connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2-22 a/d port a connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2-23 gpio port a connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2-24 gpio port b connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2-25 gpio port c connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2-26 irqa / reset / clock connector description. . . . . . . . . . . . . . . . . . . . . . . 2-30
MC56F8323EVM user manual, rev. 2 vi freescale semiconductor preliminary
preface, rev. 2 freescale semiconductor vii preliminary preface this reference manual describes in de tail the hardware on the 56f8323 evaluation module. audience this document is intended for application developers who are creating software for devices using the freescale 56f8323 part. organization this manual is organized into two chapters and two appendixes. ? chapter 1, introduction - provides an overview of the evm and its features. ? chapter 2, technical summary - describes in detail the 56f8323evm hardware. ? appendix a, 56f8323evm schematics - contains the schematics of the 56f8323evm. ? appendix b, 56f8323evm bill of material - provides a list of the materials used on the 56f8323evm board. suggested reading more documentation on the 56f8323 and th e 56f8323evm kit may be found at url: www.freescale.com
MC56F8323EVM user manual, rev. 2 viii freescale semiconductor preliminary notation conventions this manual uses the follow ing notational conventions: term or value symbol examples exceptions active high signals (logic one) no special symbol attached to the signal name a0 clko active low signals (logic zero) noted with an overbar in text and in most figures we oe in schematic drawings, active low signals may be noted by a back - slash: /we hexadecimal values begin with a ?$? symbol $0ff0 $80 decimal values no special symbol attached to the number 10 34 binary values begin with the letter ?b? attached to the number b1010 b0011 numbers considered positive unless specifically noted as a negative value 5 -10 voltage is often shown as positive: +3.3v blue text linkable on-line ...refer to chapter 7, license bold reference sources, paths, emphasis ...see: www.freescale.com
preface, rev. 2 freescale semiconductor ix preliminary definitions, acronyms, and abbreviations definitions, acronyms and abbrevia tions for terms used in this document are defined below for reference. a/d analog-to-digital; a method of converting analog signals to digital values adc analog-to-digital converter; a peripheral on the 56f8323 part can controller area network; a serial communications peripheral and method cia can in automation; an international can user?s group that coordinates standards for can communications protocols cts clear to send d/a digital-to-analog; a method of conv erting digital values to an analog form 56f8323 a 16-bit controller with motor control peripherals eonce enhanced on-chip emulation; a debug bus and port created by freescale to enable a designer to cr eate a low-cost hardware interface for a professional-quality debug environment evm evaluation module; a hardware platform which allows a customer to evaluate the silicon and develop his application flash nonvolatile random access memory flexcan flexible can interface module; a peripheral on the 56f8323 part gpio general purpose input and output port on freescale?s family of controllers; does not share pin functionallity with any other peripheral on the chip and can only be set as an input, output, or level-sensitive interrupt input ic integrated circuit jtag joint test action group; a bus protoc ol/interface used for test and debug led light emitting diode lqfp low-profile quad flat package mpio multi-purpose input and output po rt on freescale?s family of controllers; shares package pins with other peripherals on the chip and can function as a gpio
MC56F8323EVM user manual, rev. 2 x freescale semiconductor preliminary references the following sources were referenced to produce this manual: [1] dsp56800e reference manual , dsp56800erm; freescale semiconductor [2] 56f8300 peripheral user manual , mc56f8300um; freescale semiconductor [3] 56f8323 technical data , mc56f8323; freescale semiconductor [4] cia draft recommendation dr-303-1, c abling and connector pin assignment , version 1.0, can in automation [5] can specification 2.0b , bosch or can in automation once on-chip emulation, a debug bus and por t created by freescale to allow a means for low-cost hardware which provides a professional-quality debug environment pcb printed circuit board pll phase locked loop pwm pulse width modulation quad dec quadrature decoder; a peripheral on the 56f8323 part ram random access memory r/c resistor/capacitor network sram static random access memory rts request to send sci serial communications interface; a peripherial on freescale?s family of controllers spi serial peripheral interface; a peripheral on freescale?s family of controllers uart universal asynchronous receiver/transmitter ws wait state
introduction, rev. 2 freescale semiconductor 1-1 preliminary chapter 1 introduction the 56f8323evm is used to dem onstrate the abilities of the 56f 8323 and to provide a hardware tool allowing the development of a pplications that use the 56f8323. the 56f8323evm is an evaluation module boar d that includes an 56f8323 part, peripheral expansion connectors, a can interf ace, an rs-232 interf ace, a jtag-to-pc prin ter port interface and a pair of daughter card connectors. the peripheral expansion connectors and daughter card expansion connectors are for signal monitori ng and allow expansion for user features. the 56f8323evm is designed for the following purposes: ? allowing new users to become familiar with the features of the 56800e architecture. the tools and examples provided with the 56f8323evm facilitate evaluation of the feature set and the benefits of the family. ? serving as a platform for real-time software development. the tool suite enables the user to develop and simulate routines, download th e software to on-chip sram or flash, run it, and debug it using a debugger via the jtag/enhanced once (eonce) port. the breakpoint features of the eonce port enable the user to easily specify complex break conditions and to execute user-developed soft ware at full speed un til the break conditions are satisfied. the ability to examine and modi fy all user-accessible re gisters, memory and peripherals through the eonce port greatly facilitates the task of the developer. ? serving as a platform for hardware developmen t. the hardware platform enables the user to connect external hardware peripherals. the on-board peripherals can be disabled, providing the user with the ab ility to reassign any and all of the controller's peripherals. the eonce port's unobtrusive de sign means that all memory on the processor is available to the user.
MC56F8323EVM user manual, rev. 2 1-2 freescale semiconductor preliminary 1.1 56f8323evm architecture the 56f8323evm facilitates the ev aluation of various features pr esent in the 56f8323 part. the 56f8323evm can be used to develop real-time software and hardware products based on the 56f8323. the 56f8323evm provides the features necessary for a user to write and debug software, demonstrate the functionality of th at software and interface with the user's application-specific device(s). the 56f8323evm is flexible enough to allow a user to fully exploit the 56f8323's features to optimize the performance of his product, as shown in figure 1-1 . 56f8323 reset jtag / eonce spi #0 sci #1 timer c pwma +3.3v & gnd +3.3va & agnd +3.0v ref peripheral expansion connectors jtag connector parallel jtag interface dsub 25-pin dsub 9-pin pwm leds rs-232 interface power supply +3.3v, +3.3va, +5v & +3.0va 4-channel 10-bit d/a sci #0 reset logic can interface debug leds can bus header can bus daisy chain peripheral daughter card connector optional timer a adca quaddec #0 flexcan d/a header xtal/extal 8.00mhz crystal figure 1-1. block diag ram of the 56f8323evm
56f8323evm configuration jumpers introduction, rev. 2 freescale semiconductor 1-3 preliminary 1.2 56f8323evm configuration jumpers fifteen jumper groups, (jg1-jg15), shown in figure 1-2 , are used to configure various features on the 56f8323evm board. table 1-1 describes the default jumper group settings. jg6 MC56F8323EVM u3 j3 jtag p2 s/n led3 p1 y1 u1 s2 s1 p3 u9 reset irqa 1 2 jg5 jg11 jg3 jg7 jg4 jg13 jg5 1 jg7 3 jg4 pwma0 pwma1 pwma2 pwma3 pwma4 pwma5 u10 jg6 jg10 j19 j10 j18 jg8 j6 j4 j16 j14 j2 j1 j5 j21 j7 j8 j17 j9 j11 j12 j13 j15 1 jg1 3 1 jg8 3 3 4 jg12 jg3 jg9 jg10 jg2 jg11 jg9 jg2 jg1 jg12 pc0 pc1 pc2 pc3 pc4 pc5 1 2 jg15 3 4 jg13 1 jg14 3 j15 jg14 figure 1-2. 56f8323evm jumper reference
table 1-1. 56f8323evm defa ult jumper options jumper group comment jumpers connections jg1 connect on-board 8.0mhz crystal input to extal signal 1?2 jg2 connect on-board 8.0mhz crystal input to xtal signal 1?2 jg3 enable on-board parallel jt ag host/target interface nc jg4 enable rs-232 output nc jg5 pass rxd1 & txd1 signals to rs-232 level converter 1?2 & 3?4 jg6 pass temperature diode signal to ana7 input 1?2 jg7 set user jumper #0 to a 1 value 1?2 jg8 set user jumper #1 to a 1 value 1?2 jg9 spi #0 daisy chain (optional--not populated on board by default) nc jg10 can bus termination selected 1?2 jg11 connect analog ground to digital ground nc jg12 enable on-chip regulator 1?2 jg13 pass rts to cts 1?2 jg14 select +3.3v operation of on-board pa rallel jtag host/target interface 1?2 jg15 pass can_tx & can_rx signals to can tranceiver 1?2 & 3?4 MC56F8323EVM user manual, rev. 2 1-4 freescale semiconductor preliminary
56f8323evm connections introduction, rev. 2 freescale semiconductor 1-5 preliminary 1.3 56f8323evm connections an interconnection diagram is shown in figure 1-3 for connecting the pc and the external +12.0v dc/ac power supply to the 56f8323evm board. pc cable parallel extension 56f8323evm external +12v power p1 p3 connect cable to parallel / printer port with 2.1mm, receptacle connector figure 1-3. connecting the 56f8323evm cables perform the following steps to connect the 56f8323evm cables: 1. connect the parallel extension cable to the parallel port of the host computer. 2. connect the other end of the paralle l extension cable to p1, shown in figure 1-3 , on the 56f8323evm board. this connection allows th e host computer to control the board. 3. make sure that the external +12v dc, 1.2a power supply is not plugged into a +120v ac power source. 4. connect the 2.1mm output power plug from the external power supply into p3, shown in figure 1-3 , on the 56f8323evm board. 5. apply power to the external power su pply. the green power-on led, led13, will illuminate when power is correctly applied.
MC56F8323EVM user manual, rev. 2 1-6 freescale semiconductor preliminary
technical summary, rev. 2 freescale semiconductor 2-1 preliminary chapter 2 technical summary the 56f8323evm is designed as a versatile flash-based microcontrolle r development card for developing real-time software a nd hardware products to support a new generation of applications in servo and motor control; digital and wireless messaging; digital answering machines; feature phones; modems; and digital cameras. the power of the 16-bit 56f8323, combined with the on-board rs-232 interface, can interface, daught er card expansion interface and parallel jtag interface, makes the 56f8323evm ideal fo r developing and implementing many motor controlling algorithms, as well as for learning the architecture and instruction set of the 56f8323 processor. the main features of the 56f8323evm, with boa rd and schematic reference designators, include: ? mc56f8323, a 16-bit +3.3v/+2.5v processor in a 64-pin lqfp package operating at 60mhz [u1] ? 8.00mhz crystal oscillator for pr ocessor frequency generation [y1] ? optional external oscillator freque ncy input connectors [jg1 and jg2] ? joint test action group (jtag) port inte rface connector for an external debug host target interface [j3] ? on-board parallel jtag host target interf ace, with a connector for a pc printer port cable [p1], including a disable jumper [jg3] ? on-board parallel jtag host taget in terface voltage level selector [jg14] ? rs-232 interface for easy connection to a host processor [u3 and p2], with a disable jumper [jg4] ? rs-232 rts and cts signal connector [jg13] ? can interface for high speed, 1.0mbps, flexcan communications [u8 and j12] ? can bypass and bus termination [j13 and jg10] ? can signal to can transceiver isolation connector [jg15] ? peripheral daughter card expansion connector , which allows the user to attach his own sci, spi, pwm, quad decoder or gpio-com patible peripherals to the processor [j1]
MC56F8323EVM user manual, rev. 2 2-2 freescale semiconductor preliminary ? memory daughter card expansion connector, wh ich allows the user to attach additonal power and grounds[j2] ? connector which allows the user to attach his own sci #0 / mpio-compatible peripheral [j21] ? connector which allows the user to attach his own sci #1 / mpio-compatible peripheral [j17] ? connector which allows the user to attach his own spi #0 / mpio-compatible peripheral [j8] ? connector which allows the user to attach his own spi #1 / mpio-compatible peripheral [j15] ? connector which allows the user to attach his own pwma-compatible peripheral [j5] ? connector which allows the user to attach his own can physical layer peripheral [j10] ? connector which allows the user to attach his own timer a / encoder #0-compatible peripheral [j7] ? connector which allows the user to attach his own timer c-compatible peripheral [j9] ? connector which allows the user to attach his own a/d port a-compatible peripheral [j6] ? connector which allows the user to attach his own peripheral to gpio port a [j16] ? connector which allows the user to attach his own peripheral to gpio port b [j18] ? connector which allows the user to attach his own peripheral to gpio port c [j19] ? on-board power regulation from an exte rnal +12v dc-supplied power input [p3] ? light emitting diode (l ed) power indicator [led13] ? six on-board leds allow real-time de bugging of user programs [led1-6] ? six on-board port a pw m monitoring leds [led7-12] ? internal (ocr_dis) core regulator selector [jg12] ? temperature sense diode-to-ana7 selector [jg6] ? manual reset push-button [s1] ? manual interrupt push-button for irqa [s2] ? general purpose jumper on gpio pb3 [jg7] ? general purpose jumper on gpio pb0 [jg8] ? optional 4-channel 10-bit serial d/a, spi for real-time user data display [u5]
56f8323 technical summary, rev. 2 freescale semiconductor 2-3 preliminary 2.1 56f8323 the 56f8323evm uses a freescale mc56f8323 part , designated as u1 on the board and in the schematics. this part will operate at a maximum external bus speed of 60mhz. a full description of the 56f8323, including functionality and user information, is provided in these documents: ? 56f8323 technical data sheet , (mc56f8323) : electrical and timing specifications, pin descriptions, device specific peripheral in formation and package descriptions (this document) ? 56f8300 periphera l user manual , (mc56f8300um): detailed desc ription of peripherals of the 56f8300 family of devices ? dsp56800e reference manual , (dsp56800erm): detailed description of the 56800e family architecture, 16-bit core pr ocessor, and the instruction set refer to these documents for detailed informatio n about chip functionality and operation. they can be found on this url: www.freescale.com
MC56F8323EVM user manual, rev. 2 2-4 freescale semiconductor preliminary 2.2 rs-232 serial communications the 56f8323evm provides an rs-232 interface by th e use of an rs-232 level converter, maxim max3245eeai, designated as u3. refer to the rs-232 schematic diagram in figure 2-1 . the rs-232 level converter transitions the sci uart?s +3.3v signal levels to rs-232-compatible signal levels and connects to the host?s serial port via connector p2. flow control is not provided, but could be implemented using uncommitted gpio signals and connected to the rts and cts signals on jg13; see table 2-1 . the sci1 port signals can be isolated from the rs-232 level converter by removing the jumpers in jg5; reference table 2-2 . the pin-out of connector p2 is detailed in table 2-3 . the rs-232 level converter/transcei ver can be disabled by placing a jumper at jg4. 56f8323 rs-232 level converter interface txd1 rxd1 r1in t1out t2in r2out forceoff jg4 6 3 2 7 8 4 5 x 1 9 +3.3v jumper removed: enable rs-232 p2 jg13 1 2 1 2 jumper pin 1-2: disable rs-232 t1in r1out jg5 1 2 3 4 rts cts r2in t2out figure 2-1. schematic diagra m of the rs-232 interface table 2-1. flow cont rol header options jg13 pin # signal 1 rts to transceiver 2 cts from transceiver
table 2-2. sci1 jumper options jg5 pin # signal pin # signal 1 txd1 2 txd to rs-232 transceiver 3 rxd1 4 rxd from rs-232 transceiver table 2-3. rs-232 serial connector description p2 pin # signal pin # signal 1 jumper to 6 & 4 6 jumper to 1 & 4 2 txd 7 cts 3 rxd 8 rts 4 jumper to 1 & 6 9 nc 5 gnd rs-232 serial communications technical summary, rev. 2 freescale semiconductor 2-5 preliminary the 56f8323evm uses on-chip 8.00mhz relaxation oscillator or the on-board 8.00mhz crystal, y1, connected to its external crystal inpu ts, extal and xtal. to achieve its maximum internal operating frequency, the 56f8323 uses its internal pll to multiply this input clock frequency. additionally an external oscillator source can be connect ed to the device by using the oscillator bypass connectors, jg1 and jg2; see figure 2-2 . if the input frequency is above 8mhz, then the extal input should be jumper ed to ground by adding a jumper between jg1 pins 2 and 3. the input frequency would then be injected on jg2? s pin 2. if the input frequency is below 4mhz, then the input frequency can be injected on jg1?s pin 2.
56f8323 external oscillator headers jg1 1 2 3 1 2 extal xtal jg2 8.00mhz MC56F8323EVM user manual, rev. 2 2-6 freescale semiconductor preliminary figure 2-2. schematic diagra m of the clock interface six on-board light-emitting diodes, (leds), are pr ovided to allow real-time debugging for user programs. these leds will allo w the programmer to monitor pr ogram execution without having to stop the program during debugging; refer to figure 2-3 . table 2-4 describes the control of each led. table 2-4. led control controlled by user led color signal led1 red gpio port c bit 0 led2 yellow gpio port c bit 1 led3 green gpio port c bit 2 led4 red gpio port c bit 3 led5 yellow gpio port c bit 4 led6 green gpio port c bit 5
rs-232 serial communications technical summary, rev. 2 freescale semiconductor 2-7 preliminary setting pc0, pc1, pc2, pc3, pc4 or pc5 to a logic one value will turn on the associated led. 56f8323 inverting buffer pc0 pc1 pc2 green led yellow led red led +3.3v green led yellow led red led pc3 pc4 pc5 figure 2-3. schematic diagra m of the debug led interface
MC56F8323EVM user manual, rev. 2 2-8 freescale semiconductor preliminary 2.3 debug support the 56f8323evm provides an on-board paralle l jtag host target interface and a jtag interface connector for external target interf ace support. two interface connectors are provided to support each of these debuggi ng approaches. these two conn ectors are designated the jtag connector and the host parallel interface connector. 2.3.1 jtag connector the jtag connector on the 56f832 3evm allows the connection of an external host target interface for downloading programs and working with the 56f8323?s registers. this connector is used to communicate with an external host ta rget interface which passes information and data back and forth with a host pro cessor running a debugger program. table 2-5 shows the pin-out for this connector. table 2-5. jtag c onnector description j3 pin # signal pin # signal 1 tdi 2 gnd 3 tdo 4 gnd 5 tck 6 gnd 7 nc 8 key 9 reset 10 tms 11 +3.3v 12 nc 13 de 14 trst when this connector is used w ith an external host target interface, the parallel jtag interface should be disabled by placing a jumper in jumper block jg3. refer to table 2-6 for this jumper?s selection options. table 2-6. parallel jtag inte rface disable jumper selection jg3 comment no jumpers enable on-board parallel jtag interface 1?2 disable on-board parallel jtag interface
debug support technical summary, rev. 2 freescale semiconductor 2-9 preliminary 2.3.2 parallel jtag interface connector the parallel jtag interface connector, p1, allows the 56f8323 to communi cate with a parallel printer port on a windows pc; reference figure 2-4 . using this connector, the user can download programs and work with the 56f8323?s registers. table 2-7 shows the pin-out for this connector. when using the parallel jtag interf ace, the jumper at jg3 should be removed, as shown in table 2-6 . a jumper at jg14 selects the parall el printer port?s interface voltage between +3.3v and +5.0v; see table 2-8 . db-25 connector parallel jtag interface 56f8323 tdi tdo p_trst tms tck p_reset out out out out out out in in in in in in en tdi tdo trst tms tck reset jg3 1 2 +3.3v jumper removed: enable jtag i/f jumper pin 1-2: disable jtag i/f p_de out in de figure 2-4. block diagram of the parallel jtag interface
table 2-7. parallel jtag in terface connector description p1 pin # signal pin # signal 1 nc 14 nc 2 port_reset 15 port_ident 3 port_tms 16 n/c 4 port_tck 17 n/c 5 port_tdi 18 gnd 6 port_ trst 19 gnd 7 port_de 20 gnd 8 port_ident 21 gnd 9 port_vcc 22 gnd 10 nc 23 gnd 11 port_tdo 24 gnd 12 nc 25 gnd 13 port_connect table 2-8. parallel jtag inte rface voltage selection jumper jg14 comment 1?2 +3.3v parallel printer port interface 2?3 +5.0v parallel printer port interface MC56F8323EVM user manual, rev. 2 2-10 freescale semiconductor preliminary
reset technical summary, rev. 2 freescale semiconductor 2-11 preliminary 2.4 external interrupts one on-board push-button switch is provided for external inte rrupt generation, as shown in figure 2-5 . s2 allows the user to generate a hardware interrupt for signal line irqa . this switch allows the user to generate interrupts for user-specific programs. 56f8323 irqa +3.3v 10k s2 0.1f figure 2-5. schematic diagram of the user interrupt interface 2.5 reset logic is provided on the 56f8323 to generate an internal power-on reset. additional reset logic is provided to support the reset signal s from the jtag connector, the parallel jtag interface and the user reset push-button, s1; refer to figure 2-6 . reset pushbutton manual reset jtag_tap_reset jtag_reset reset trst s1 figure 2-6. schematic diagra m of the reset interface
MC56F8323EVM user manual, rev. 2 2-12 freescale semiconductor preliminary 2.6 power supply the main power input to the 56f8323evm, +12v dc at 1.2a, is through a 2.1mm coax power jack. this input power is rectifie d to provide a dc supply input. this allows a user the option to use a +12v ac power supply. a 1.2amp power supply is provided w ith the 56f8323evm; however, less than 500ma is required by the evm. the remaining current is available for custom control applications when connected to th e daughter card connectors. the 56f8323evm provides +5.0v dc regulation for the ca n interface and additional regulators. the 56f8323evm provides +3.3v dc voltage regulatio n for the processor, memory, d/a, adc, parallel jtag interface and supporting logic; refer to figure 2-7 . additional voltage regulation logic provides a low noise +3.0v dc voltage reference to the controller?s a/d v refh . optionally, the processor?s a/d v refh voltage can be provided by the +3.3va supply on the board by removing u15 and addi ng a 10 ohm resistor at r83. a jumper, jg11, and resistor, r68, are provided to allow the analog and digital grounds to be isolated on the 56f8323evm board. this allows the analog ground reference point to be provided on a custom board attached to the 56f8323evm?s daughter card connectors. by removing r68, the agnd reference is disconnected from the 56f8323evm?s digital gr ound. by placing a jump er in jg11 or by reinstalling r68, the agnd is r econnected to the 56f8323evm?s digital ground. power applied to the 56f8323evm is indicated with a powe r-on led, referenced as led13. optionally, the user can provide the +2.5 dc voltage needed by the controller?s core on connector j14 and disable the on-chip core voltage regulator by removing the jumper on jg 12. additonally, four 0 ohm resistors or shorting wires must be added at r70, r71, r72 and r73, to allow the external +2.5v dc to pass to the 56f8323.
+5.0v dc +12v dc/ac power condition can 56f8323 v dd_io & pll +3.3v regulator p3 56f8323evm parts 56f8323 v refh +3.3v dc +3.0va dc +5.0v regulator 56f8323 adca +3.3v regulator +3.3va dc 56f8323 v dd core +2.5v dc ext in 1 2 j14 u15 r70-r73 r67 10 ? bridge rectifier input +3.0v regulator power on power supply technical summary, rev. 2 freescale semiconductor 2-13 preliminary figure 2-7. schematic diag ram of the power supply
MC56F8323EVM user manual, rev. 2 2-14 freescale semiconductor preliminary 2.7 daughter card connectors the evm board contains two daughter card expans ion connectors. one connector, j1, contains the processor?s peripheral port signals. the sec ond connector, j2, contains addional power and ground signals. 2.7.1 peripheral daughter card expansion connector the processor?s peripheral port signals are connect ed to the peripheral daughter card expansion connector, j1. the peripheral daughter card c onnector is used to connect a user-specific daughter card to the processor?s peripheral po rt signals. the peripheral port daughter card connector is a 100-pin high-density connector wi th signals for the irqs , reset, spi, sci, pwm, adc and quad timer ports. table 2-9 shows the peripheral daughter card connector?s signal-to-pin assignments. table 2-9. peripheral daughte r card connector description j1 pin # signal pin # signal 1 +12v 2 +12v 3 gnd 4 gnd 5 +5.0v 6 +5.0v 7 gnd 8 gnd 9 +3.3v 10 +3.3v 11 gnd 12 gnd 13 nc 14 nc 15 nc 16 nc 17 gnd 18 gnd 19 phasea0 / pb7 / ta0 20 phaseb0 / pb6 / ta1 21 index0 / pb5 / ta2 22 home0 / pb4 / ta3 23 tc0 24 ss0 25 tc0 26 ss0 27 tc1 28 miso0
daughter card connectors technical summary, rev. 2 freescale semiconductor 2-15 preliminary 29 irqa 30 nc 31 tc1 32 tc3 33 pwma0 34 pwma1 35 pwma2 36 pwma3 37 pwma4 38 pwma5 39 gnd 40 gnd 41 isa0 42 isa1 43 isa2 44 gnd 45 faulta1 46 faulta0 47 nc 48 faulta2 49 gnd 50 gnd 51 nc 52 miso0 53 nc 54 nc 55 nc 56 nc 57 gnd 58 gnd 59 nc 60 nc 61 nc 62 ss0 63 nc 64 nc 65 nc 66 nc 67 mosi0 68 ss0 69 tc0 70 tc1 71 sclk0 72 tc0 73 can_tx 74 can_rx 75 mosi0 76 miso0 77 sclk0 78 ss0 table 2-9. peripheral daughter ca rd connector descr iption (continued) j1 pin # signal pin # signal
MC56F8323EVM user manual, rev. 2 2-16 freescale semiconductor preliminary 79 gnd 80 gnd 81 +v refh 82 +v refh 83 gnda 84 gnda 85 nc 86 nc 87 nc 88 nc 89 nc 90 nc 91 nc 92 nc 93 an0 94 an1 95 an2 96 an3 97 an4 98 an5 99 an6 100 an7 table 2-9. periphera l daughter card connector description (continued) j1 pin # signal pin # signal
daughter card connectors technical summary, rev. 2 freescale semiconductor 2-17 preliminary 2.7.2 memory daughter card expansion connector additional power and ground signals are connected to the memory daughter card expansion connector, j2. table 2-10 shows the port signal-to-pin assignments. table 2-10. memory daughter card connector description j2 pin # signal pin # signal 1 nc 2 nc 3 nc 4 nc 5 nc 6 nc 7 nc 8 nc 9 gnd 10 gnd 11 nc 12 nc 13 nc 14 nc 15 nc 16 nc 17 nc 18 nc 19 gnd 20 gnd 21 gnd 22 gnd 23 nc 24 nc 25 nc 26 nc 27 nc 28 nc 29 nc 30 nc 31 gnd 32 gnd 33 gnd 34 gnd 35 nc 36 nc 37 nc 38 nc 39 nc 40 nc 41 nc 42 nc
MC56F8323EVM user manual, rev. 2 2-18 freescale semiconductor preliminary 43 gnd 44 gnd 45 nc 46 nc 47 nc 48 nc 49 nc 50 nc 51 nc 52 gnd 53 gnd 54 gnd 55 +3.3v 56 +3.3v 57 gnd 58 gnd 59 +5.0v 60 +5.0v table 2-10. memory daughter ca rd connector description (continued) j2 pin # signal pin # signal
serial 10-bit 4-channel d/ a converter (optional) technical summary, rev. 2 freescale semiconductor 2-19 preliminary 2.8 serial 10-bit 4-chan nel d/a converter (optional) the 56f8323evm board contains the provions for a user to provide a serial 10-bit, 4-channel d/a converter connected to the 56f8323?s spi #0 port. the output pins are uncommitted and are connected to a 4x2 header, j4, to a llow easy user connections. refer to figure 2-8 for the d/a connections and table 2-11 for the header?s pin-out. the d/a?s output full-scale range value can be set to a value from +0.0v to +2.4v by a trimpot , r48. if this trimpot is preset to +2.05v, it would provide approximately +2 mv per step. if another device must be used with spi #0?s miso signal and with the d/a converter on the board, the daisy chain jumper, jg9, can be used to extend or isolate the serial chain. 1 3 5 7 2 4 6 8 d/a connector d/a 0 d/a 1 d/a 2 d/a 3 +3.3va r48 v ref max5251 din dout sclk cs cl mosi0 1 2 miso0 sclk0 ss0 jg9 56f8323 rsto figure 2-8. serial 10-bit, 4-channel d/a converter table 2-11. d/a h eader description j4 pin # signal pin # signal 1 d/a channel 0 2 agnd 3 d/a channel 1 4 agnd 5 d/a channel 2 6 agnd 7 d/a channel 3 8 agnd
MC56F8323EVM user manual, rev. 2 2-20 freescale semiconductor preliminary 2.9 motor control pwm signals and leds the 56f8323 has one pwm unit. th is unit contains six pwm out put signals, three fault input signals and three phase current sense inputs. the pwm signals ar e connected to a set of six pwm leds via inverting buffers. the buffers are used to isolat e and drive the processor?s pwm outputs to the pwm leds. the pwm leds indi cate the status of pwm signals; refer to figure 2-9 . additionally, the pwm signals are routed out to a header, j5, and to the peripheral daughter card connector, j1, fo r easy use by the end user. led +3.3v led9 56f8323 led10 led11 led12 led7 led8 pwma0 pwma1 pwma2 pwma3 pwma5 buffer pwma0 yellow led pwma1 pwma2 pwma3 pwma4 pwma5 green led yellow led green led yellow led green led phase a top phase a bottom phase b top phase b bottom phase c top phase c bottom pwma4 figure 2-9. pwm interface and leds
can interface technical summary, rev. 2 freescale semiconductor 2-21 preliminary 2.10 can interface the 56f8323evm board contains a can physical-lay er interface chip that is attached to the flexcan port?s can_rx and can_tx pins on the 56f8323. the evm board uses a philips high-speed, 1.0mbps, physical layer interface chip, pca82c250. due to the +5.0v operating voltage of the can interface chi p, a pull-up to +5.0v is required to level shift the transmit data output line from the 56f8323. the can_tx and can_rx signals from the processor can be isolated by the connector at jg15; see table 2-12 . the canh and canl signals pass through inductors before attaching to the can bus c onnectors. a primary, j12, and daisy chain, j13, can connectors are provided to allow easy daisy chaining of can devices. can bus termination of 120 ohms can be provided by adding a jumper to jg10. refer to table 2-13 for the can connector signals and to figure 2-10 for a connection diagram. 56f8323 +5.0v can transceiver j12 daisy chain can connector j13 can bus connector can bus terminator jg10 120 pca82c250t 1k can_tx can_rx 1 2 3 4 5 4 3 5 canh canl txd rxd jg15 1 3 4 2 figure 2-10. can interface table 2-12. can signal isolation jumper options jg15 pin # signal pin # signal 1 can_tx 2 can_tx to can transceiver 3 can_rx 4 can_rx from can transceiver
table 2-13. can header description j12 and j13 pin # signal pin # signal 1 nc 2 nc 3 canl 4 canh 5 gnd 6 nc 7 nc 8 nc 9 nc 10 nc MC56F8323EVM user manual, rev. 2 2-22 freescale semiconductor preliminary 2.11 software feature jumpers the 56f8323evm board contains two software f eature jumpers that allow the user to select ?user-defined? software features. two gpio por t pins, pb3 and pb0, are pulled high or low with 10k ohm resistors on jg7 and jg8, respectively. attaching a jumper betw een pins 1 and 2 will place a high, or 1, on the port pin. attaching a jumper between pins 2 and 3 will place a low, or 0, on the port pin; see figure 2-11 . 56f8323 jg7 user jumper #0 1 2 3 10k 10k +3.3v jg8 user jumper #1 1 2 3 10k 10k +3.3v sclk0 / pb3 ss0 / pb0 figure 2-11. software feature jumpers
peripheral expansion connectors technical summary, rev. 2 freescale semiconductor 2-23 preliminary 2.12 peripheral expansion connectors the evm board contains a group of peripheral e xpansion connectors used to gain access to the resources of the 56f8323. the following si gnal groups have expansion connectors: ?pwm port a ? serial peripheral interface port #0 ? serial peripheral interface port #1 ? serial communications port 0 ? serial communications port 1 ? encoder #0 / timer channel a ? timer channel c ? flexcan port ? a/d input port a ?gpio port a ?gpio port b ?gpio port c ? irqa / reset / clock 2.12.1 pwm port a expansion connector the pwm port a is attached to this connector. refer to table 2-14 for connection information. table 2-14. pwm port a connector description j5 pin # signal pin # signal 1 pwma0 / pa0 2 pwma1 / pa1 3 pwma2 / pa2 / ss1 4 pwma3 / pa3 / miso1 5 pwma4 / pa4 / mosi1 6 pwma5 / pa5 / sclk1 7 faulta0 / pa6 8 faulta1 / pa7 9 faulta2 / pa8 10 nc 11 isa0 / pa9 12 isa1 / pa10 13 isa2/pa11 14 gnd
MC56F8323EVM user manual, rev. 2 2-24 freescale semiconductor preliminary 2.12.2 serial peripheral in terface #0 expa nsion connector the serial peripheral interface #0 is an mpio por t attached to this connector. this port can be configured as a serial peripheral interface or as a general purpose i/o port. refer to table 2-15 for connection information. table 2-15. spi #0 c onnector description j8 pin # signal pin # signal 1 mosi0 / pb2 2 miso0 / pb1 / rxd1 3 sclk0 / pb3 4 ss0 / pb0 / txd1 5 gnd 6 +3.3v 2.12.3 serial peripheral in terface #1 expa nsion connector the serial peripheral interface #1 is an mpio por t attached to this connector. this port can be configured as a serial peripheral interface or as a general purpose i/o port. refer to table 2-16 for the connection information. table 2-16. spi #1 c onnector description j15 pin # signal pin # signal 1 mosi1 / pwma4 2 miso1 / pwma3 3 sclk1 / pwma5 4 ss1 / pwma2 5 gnd 6 +3.3v
peripheral expansion connectors technical summary, rev. 2 freescale semiconductor 2-25 preliminary 2.12.4 serial communications port #0 expansion connector the serial communications port #0 is an mpio port attached to the sci #0 expansion connector. this port can be configured as a serial communi cations interface or as timer port c channels. refer to table 2-17 for connection information. table 2-17. sci #0 connector description j21 pin # signal pin # signal 1 txd0 / tc0 2 rxd0 / tc1 3 gnd 4 +3.3v 5 gnd 6 +5.0v 2.12.5 serial communications port #1 expansion connector the serial communications port #1 is an mpio port attached to the sci #0 expansion connector. this port can be configured as a serial communi cations interface or as spi0 signals. refer to table 2-18 for connection information. table 2-18. sci #1 connector description j17 pin # signal pin # signal 1 txd1 / ss0 2 rxd1 / miso0 3 gnd 4 +3.3v 5 gnd 6 +5.0v
MC56F8323EVM user manual, rev. 2 2-26 freescale semiconductor preliminary 2.12.6 encoder #0 / quad ti mer channel a expansion connector the encoder #0 / quad timer cha nnel a port is an mpio port a ttached to the timer a expansion connector. this port can be configured as a quad rature decoder interface port, as a quad timer port, or as gpio. refer to table 2-19 for the signals attached to the connector. table 2-19. timer a signa l connector description j7 pin # signal pin # signal 1 phasea0 / ta0 / pb7 2 phaseb0 / ta1 / pb6 3 index0 / ta2 / pb5 4 home0 / ta3 / pb4 5 gnd 6 +3.3v 2.12.7 timer channel c expansion connector the timer channel c port is an mpio port attach ed to the timer c expansion connector. this port can be configured as a quad timer interf ace, as sci0 signals, or as gpio. refer to table 2-20 for the signals attached to the connector. table 2-20. timer channel c connector description j9 pin # signal pin # signal 1 tc0 / txd0 / pc6 2 tc1 / rxd0 / tc5 3 gnd 4 tc3 / pc4
peripheral expansion connectors technical summary, rev. 2 freescale semiconductor 2-27 preliminary 2.12.8 flexcan expansion connector the flexcan port is an mpio port attached to the flexcan expansion connector. this port can be configured as a flexcan interface or as gpio. refer to table 2-21 for connection information. table 2-21. can conn ector description j10 pin # signal pin # signal 1 can_tx / pc3 2 gnd 3 can_rx / pc2 4 gnd 2.12.9 a/d port a expansion connector the 8-channel analog-to-digital conversion port a is attached to this connector. refer to table 2-22 for connection information. there is an rc network on each of the analog port a input signals; see figure 2-12 . table 2-22. a/d port a connector description j6 pin # signal pin # signal 1 an0 2 an1 3 an2 4 an3 5 an4 6 an5 7 an6 8 an7 9 gnda 10 +v refh
to controller analog port 100 ohm analog input 0.0022f MC56F8323EVM user manual, rev. 2 2-28 freescale semiconductor preliminary figure 2-12. typical an alog input rc filter 2.12.10 gpio port a expansion connector the gpio port a is attached to this connector. refer to table 2-23 for connection information. table 2-23. gpio port a connector description j16 pin # signal pin # signal 1 pa0 / pwma0 2 pa1 / pwma1 3 pa2 / pwma2 / ss1 4 pa3 / miso1 / pwma3 5 pa4 / pwma4 / mosi1 6 pa5 / sclk1 / pwma5 7 pa6 / faulta0 8 pa7 / faulta1 9 pa8 / faulta2 10 pa9 / isa0 11 pa10 / isa1 12 pa11 / isa2 13 gnd 14 +3.3v
peripheral expansion connectors technical summary, rev. 2 freescale semiconductor 2-29 preliminary 2.12.11 gpio port b expansion connector the gpio port b is attached to this connector. refer to table 2-24 for connection information. table 2-24. gpio port b connector description j18 pin # signal pin # signal 1 pb0 / ss0 2 pb1 / miso0 3 pb2 / mosi0 4 pb3 / sclk0 5 pb4 / home0 6 pb5 / index0 7 pb6 / phaseb0 8 pb7 / phasea0 9 gnd 10 +3.3v 2.12.12 gpio port c expansion connector the gpio port c is attached to this connector. refer to table 2-25 for connection information. table 2-25. gpio port c connector description j19 pin # signal pin # signal 1 pc0 / extal 2 pc1 / xtal 3 pc2 / can_rx 4 pc3 / can_tx 5 pc4 / tc3 6 pc5 / tc1 7 pc6 / tc0 8 nc 9 gnd 10 +3.3v
MC56F8323EVM user manual, rev. 2 2-30 freescale semiconductor preliminary 2.12.13 irqa / reset / clock expansion connector the irqa / reset / clock signals are a ttached to this connector. refer to table 2-26 for connection information. table 2-26. irqa / reset / clock connector description j11 pin # signal pin # signal 1 irqa 2 reset 3 extal / pc0 4 xtal / pc1 9 gnd 10 +3.3v 2.13 test points the 56f8323evm board has a total of eleven test points: ? analog ground (agnd) [tp4] ? four digital grounds (gnd) [tp1, tp2, tp3 & tp10] ? two +3.3v [tp6 & tp11] ? +3.3va [tp5] ? two +5.0v [tp7 & tp8] ? +12v [tp9]
56f8323evm schematics, rev. 2 freescale semiconductor appendix a-1 preliminary appendix a 56f8323evm schematics
a a b b c c d d e e 4 4 3 3 2 2 1 1 single trace to gnda single trace to gnda on-chip core regulator 1-2 n/c enable re gulator disable re gulator dspo design mc56f8323 processor MC56F8323EVM.dsn 1.1 1 13 monday, may 12, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 faulta2 faulta1 faulta0 vrefp vrefm vrefn ana7 temp_sense vcap3 vcap2 vcap1 vcap4 vcap1 vcap3 vcap4 vcap2 ocr_dis ocr_dis vdd_io4 vdd_io3 vdd_io2 vdd_io1 vdd_io3 vdd_io2 vdd_io1 vdd_io4 va pwma1 pwma2 pwma5 isa1 isa0 isa2 faulta0 faulta1 faulta2 pwma0 pwma4 pwma3 phasea0 home0 index0 phaseb0 ana6 ana0 ana7 ana2 ana1 ana5 ana4 ana3 /irqa extal xtal /reset tdi tdo tms /trst tck miso0 /ss0 sclk0 mosi0 tc1 tc3 tc0 can_rx can_tx +3.3va +vrefh +3.3v_pll vddcore +3.3v +3.3v r15 47k r16 47k r17 47k c5 0.1uf c41 0.001uf c42 100pf c8 0.1uf c7 0.1uf c6 0.1uf jg6 1 2 r70 0 ohm dnp r71 0 ohm dnp r72 0 ohm dnp r73 0 ohm dnp c1 2.2uf c2 2.2uf c3 2.2uf c4 2.2uf jg12 1 2 r74 1k u1 mc56f8323fg60 12 3 4 7 8 9 10 13 14 15 47 46 2 16 18 19 26 27 28 29 30 31 32 33 34 64 63 1 58 53 54 55 56 21 25 22 24 62 61 52 51 50 49 57 23 5 43 6 20 48 59 11 44 17 60 45 42 41 40 39 37 38 36 35 irqa pwma0/pa0 pwma1/pa1 pwma2/ss1/pa2 pwma3/miso1/pa3 pwma4/mosi1/pa4 pwma5/sclk1/pa5 faulta0/pa6 faulta1/pa7 faulta2/pa8 xtal/pc1 extal/pc0 reset isa0/pa9 isa1/pa10 isa2/pa11 ana0 ana1 ana2 ana3 ana4 ana5 ana6 ana7 temp_sense tc1/rxd0/pc5 tc3/pc4 tc0/txd0/pc6 trst tck tms tdi tdo ss0/txd1/pb0 sclk0/pb3 miso0/rxd1/pb1 mosi0/pb2 can_tx/pc3 can_rx/pc2 pha0/ta0/pb7 phb0/ta1/pb6 index0/ta2/pb5 home0/ta3/pb4 vcap1 vcap2 vcap3 vcap4 vdd_io1 vdd_io2 vdd_io3 vdd_io4 vss_io1 vss_io3 vss_io2 vss_io4 ocr_dis vdaa_osc_pll vdda_adc vrefh vssa_adc vrefp vreflo vrefmid vrefn r79 0 ohm r77 0 ohm r78 0 ohm r76 0 ohm r80 0 ohm MC56F8323EVM user manual, rev. 2 appendix a-2 freescale semiconductor preliminary figure a-1. 56f8323 processor
a a b b c c d d e e 4 4 3 3 2 2 1 1 12 3 ds1818 irqa pushbutton user software feature jumpers #0 jumper jumper #1 user osc bypass reset pushbutton optional gpiob3 gpiob0 gpioc0 gpioc1 dspo design reset, clock & irq MC56F8323EVM.dsn 1.1 213 monday, may 12, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 /por /irqa sclk0 /ss0 /por extal xtal +3.3v +3.3v +3.3v +3.3v +3.3v c9 0.1uf r24 10k s2 jg7 1 2 3 r25 10k r26 1k r28 1k r27 10k jg8 1 2 3 y1 8.00mhz r14 1m u2 ds1818 dnp 2 1 3 vcc rst gnd r23 10k jg2 1 2 jg1 1 2 3 s1 56f8323evm schematics, rev. 2 freescale semiconductor appendix a-3 preliminary figure a-2. reset, clock & irq
a a b b c c d d e e 4 4 3 3 2 2 1 1 rs-232 shutdown jumper 1 - 2 n/c rs-232 enable rs-232 disable connector cts dsr dtr rxd txd rts dcd sci #1 rs-232 rts/cts dspo design rs-232 and sci connectors MC56F8323EVM.dsn 1.1 3 13 monday, may 12, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 r4in r5in r3in t3in /en t3in /en r3in r4in r5in txd txd1 rxd1 rts1 cts1 cts rts rxd /ss0 miso0 +3.3v +3.3v +3.3v r35 1k r36 1k r34 1k r32 1k r30 1k c32 1.0uf c33 1.0uf c35 1.0uf c34 1.0uf jg4 1 2 r29 1k 1 1 1 1 1 1 jg5 1 3 2 4 u3 max3245eeai 27 1 26 2 23 28 14 13 12 19 18 17 16 15 8 7 6 5 4 11 10 9 22 24 3 25 20 21 v+ c2+ vcc c2- forceon c1+ t1in t2in t3in r1out r2out r3out r4out r5out r5in r4in r3in r2in r1in t3out t2out t1out forceoff c1- v- gnd r2outb invalid jg13 1 2 p2 5 9 4 8 3 7 2 6 1 MC56F8323EVM user manual, rev. 2 appendix a-4 freescale semiconductor preliminary figure a-3. rs-232 and sci connectors
a a b b c c d d e e 4 4 3 3 2 2 1 1 serial d/a connector set to 2.7v spi0 daisychain optional dspo design debug serial 4-channel d/a converter MC56F8323EVM.dsn 1.1 413 monday, may 12, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 +vref d/a1 d/a3 d/a2 d/a0 sclk0 mosi0 /ss0 /reset miso0 +3.3v +3.3v +3.3va +vref r58 5.1k dnp u5 max5251beap dnp 1 2 3 4 5 6 15 16 17 18 19 20 13 9 12 10 8 7 14 11 agnd fba outa outb fbb refab refcd fbc outc outd fbd vdd up0 din dout sclk cs cl pdl dgnd j4 dnp 1 3 5 7 2 4 6 8 1 r48 1k pot dnp jg9 dnp 1 2 56f8323evm schematics, rev. 2 freescale semiconductor appendix a-5 preliminary figure a-4. debug serial 4- channel d/a converter
a a b b c c d d e e 4 4 3 3 2 2 1 1 pwm state leds yellow led yellow led green led green led green led yellow led pa0 pa1 pa2 pa3 pa4 pa5 dspo design pwm port a state leds MC56F8323EVM.dsn 1.1 513 monday, may 12, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 pwma4 pwma1 pwma0 pwma5 pwma2 pwma3 +3.3v r7 270 r8 270 r9 270 r10 270 r11 270 u6a 74ac04 1 2 u6b 74ac04 3 4 u6c 74ac04 5 6 u6d 74ac04 9 8 u6e 74ac04 11 10 u6f 74ac04 13 12 led7 led8 led9 led10 led11 led12 r12 270 MC56F8323EVM user manual, rev. 2 appendix a-6 freescale semiconductor preliminary figure a-5. pwm port a state leds
a a b b c c d d e e 4 4 3 3 2 2 1 1 user leds pc3 pc1 pc2 pc0 red led yellow led green led red led pc4 pc5 yellow led green led dspo design user debug leds MC56F8323EVM.dsn 1.1 6 13 monday, may 12, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 can_tx can_rx xtal extal tc1 tc3 +3.3v u7b 74ac04 3 4 u7c 74ac04 5 6 u7d 74ac04 9 8 r3 270 r2 270 led1 r1 270 u7a 74ac04 1 2 led3 led2 led4 u7e 74ac04 11 10 u7f 74ac04 13 12 r6 270 led6 led5 r4 270 r5 270 56f8323evm schematics, rev. 2 freescale semiconductor appendix a-7 preliminary figure a-6. user debug leds
a a b b c c d d e e 4 4 3 3 2 2 1 1 pb4/ta3 pb5/ta2 pb6/ta1 spi #0 pwma pb7/ta0 pb0/txd1 pb1/rxd1 txd1 rxd1 pa2/ss1 pa4/mosi1 pa3/miso1 pa5/sclk1 quad decoder #0 pa0 pa6 pa8 pa9 pa11 pa1 pa7 pa10 & timer channel a pb2 pb3 sci #1 spi #1 /ss1 miso1 mosi1 sclk1 gpio port a pa2 pa4 pa3 pa5 pa0 pa6 pa8 pa1 pa7 pa10 pa9 pa11 gpio port b pb1 pb0 pb2 pb3 pb4 pb6 pb5 pb7 pc3 pc4 irq, reset sci #0 a/d port a txd0 pc2 can pc4 & sci #0 pc3 pc2 pc0 pc1 pc6/txd0 pc0 pc5/rxd0 pc6 & gpio port c pc5 pc1 rxd0 & clock timer channel c gpio port c spare spare dspo design dsp port expansion connectors MC56F8323EVM.dsn 1.1 7 13 monday, may 12, 2003 b dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 pwma0 pwma2 pwma4 pwma1 pwma3 pwma5 faulta0 faulta2 faulta1 isa0 isa1 isa2 mosi0 miso0 sclk0 /ss0 index0 home0 phaseb0 phasea0 /ss0 miso0 pwma4 pwma3 pwma5 pwma2 pwma0 pwma2 pwma4 pwma1 pwma3 pwma5 faulta0 faulta2 faulta1 isa1 isa0 isa2 miso0 sclk0 /ss0 mosi0 home0 phaseb0 index0 phasea0 tc1 extal an7 tc1 an3 an5 /irqa can_rx tc0 an4 tc0 an2 can_tx an6 xtal tc3 tc3 an0 an1 tc1 can_tx /reset tc0 can_rx extal xtal +3.3v +3.3v +3.3v +3.3v +3.3v +5.0v +3.3v +5.0v +3.3v +3.3v +3.3v +vrefh j5 1 3 5 7 9 11 13 2 4 6 8 10 12 14 j8 1 3 5 2 4 6 j7 1 3 5 2 4 6 1 j15 1 3 5 2 4 6 j16 1 3 5 7 9 11 13 2 4 6 8 10 12 14 j17 1 3 5 2 4 6 j18 1 3 5 7 9 2 4 6 8 10 j6 1 3 5 7 9 2 4 6 8 10 j11 1 3 5 2 4 6 1 j9 1 3 2 4 j19 1 3 5 7 9 2 4 6 8 10 j21 1 3 5 2 4 6 j10 1 3 2 4 MC56F8323EVM user manual, rev. 2 appendix a-8 freescale semiconductor preliminary figure a-7. port ex pansion connectors
a a b b c c d d e e 4 4 3 3 2 2 1 1 daughter peripheral port connector pc6 pc5 pb0/txd1 pc4 pb0 pb0 gnd gnd gnd gnd gnd gnd gnd gnd td1 td0 pb2 pb3 rxd1 txd1 rxd0 txd0 daughter address/data connector ta2 ta0 ta3 pc5 pc6 ta1 pb1 dspo design daughter card connector MC56F8323EVM.dsn 1.1 8 13 monday, may 12, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnda gnd gnd gnda gnd gnd gnd gnd gnd gnd gnda gnd gnd gnd /ss0 tc1 tc0 miso0 /irqa can_tx can_rx tc0 /ss0 tc1 mosi0 miso0 tc0 sclk0 /ss0 sclk0 mosi0 /ss0 tc3 tc0 tc1 phasea0 index0 phaseb0 home0 pwma0 pwma2 pwma4 pwma1 pwma3 pwma5 faulta1 faulta0 faulta2 isa2 isa0 isa1 an6 an0 an2 an4 an1 an7 an5 an3 /ss0 miso0 +vrefh +12v +12v +vrefh +5.0v +3.3v +5.0v +3.3v +3.3v +5.0v +5.0v +3.3v j2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 51 52 53 54 55 56 57 58 59 60 j1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 56f8323evm schematics, rev. 2 freescale semiconductor appendix a-9 preliminary figure a-8. daughter card connectors
a a b b c c d d e e 4 4 3 3 2 2 1 1 can bus connector daisy-chain can bus connector can bus termina tion can se lect dspo design high-speed can interface MC56F8323EVM.dsn 1.1 913 saturday, june 28, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 canl bcanh bcanl bcanh bcanl bcanl bcanh canh bcanh bcanl can_tx can_rx +5.0v +5.0v u8 pca82c250t 1 4 2 3 5 6 7 8 txd rxd gnd vcc vref canl canh slope r37 1k 1 j12 1 3 5 7 9 2 4 6 8 10 j13 1 3 5 7 9 2 4 6 8 10 jg10 1 2 r38 120 1/4w l1 jg15 1 3 2 4 MC56F8323EVM user manual, rev. 2 appendix a-10 freescale semiconductor preliminary figure a-9. high-sp eed can interface
a a b b c c d d e e 4 4 3 3 2 2 1 1 parallel jtag interface key jtag connector on-board host target interface disable port_de port_vcc dspo design parallel jtag host target interface and jtag connector MC56F8323EVM.dsn 1.1 10 13 friday, june 20, 2003 b dsp standard products division 2100 east elliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 p_reset /j_trst /j_reset tdo p_reset tms tck /j_trst port_tdo port_tms /port_trst port_tck port_tdi port_connect port_reset port_ident /j_reset /j_trst /de p_de /j_trst pwr /de tdi pwr tdo p_de port_pu port_connect port_pu /j_reset tdi tdo tck tms /reset /trst /por +3.3v +3.3v +3.3v +3.3v +5.0v +3.3v +vsel +vsel r47 5.1k r46 5.1k j3 1 3 5 7 9 11 13 2 4 6 8 10 12 14 r22 47k r18 47k jg3 1 2 p1 1 3 2 15 14 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 r57 51 ohm q1 2n2222a u11a 74ac00 1 2 3 u11c 74ac00 9 10 8 u11b 74ac00 4 5 6 u11d 74ac00 12 13 11 r44 5.1k r21 47k r19 47k r20 47k 1 r45 5.1k 1 r42 5.1k r43 5.1k r41 5.1k u9 mc74hc244dw 18 16 14 12 9 7 5 3 19 1 2 4 6 8 11 13 15 17 20 10 1y1 1y2 1y3 1y4 2y1 2y2 2y3 2y4 2g 1g 1a1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 vcc gnd u10 mc74lcx244dw 18 16 14 12 9 7 5 3 19 1 2 4 6 8 11 13 15 17 20 10 1y1 1y2 1y3 1y4 2y1 2y2 2y3 2y4 2g 1g 1a1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 vcc gnd r53 0 ohm r51 0 ohm r52 0 ohm r55 0 ohm r54 0 ohm r56 51 ohm jg14 1 2 3 r81 1k r82 1k dnp 56f8323evm schematics, rev. 2 freescale semiconductor appendix a-11 preliminary figure a-10. parallel jtag host ta rget interface and jtag connector
a a b b c c d d e e 4 4 3 3 2 2 1 1 note: use a single trace for gnda signals to the common gnda point. dspo design a/d input filters MC56F8323EVM.dsn 1.1 11 13 monday, may 12, 2003 a dsp standard products division 2100 east e lliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 ana7 ana0 ana1 ana2 ana3 ana4 ana5 ana6 an0 an1 an2 an3 an4 an5 an6 an7 c49 0.0022uf c51 0.0022uf c53 0.0022uf c55 0.0022uf c50 0.0022uf c52 0.0022uf c54 0.0022uf c56 0.0022uf r66 100 r59 100 r61 100 r63 100 r65 100 r60 100 r62 100 r64 100 MC56F8323EVM user manual, rev. 2 appendix a-12 freescale semiconductor preliminary figure a-11. a/d input filters
a a b b c c d d e e 4 4 3 3 2 2 1 1 external power input 7-12v dc/ac 12 3 4 mc33269 3.3v and 5.0v regulator test point power good led note: remove 0 ohm resistor to use analog gnd isolation jumper. single trace to gnda. 1 2 34 reg113na3/3k 3.0v ref regulator 5 +3.0v +3.3v +3.3va ground analog ground +5.0v test point test point ground test point ground test point test point test point test point +3.3v +12.0v test point +5.0v test point ground test point external vddcore input note: to use, provide +2.5vdc on pin-1. add 0 ohm resistors for vcap1, vcap2, vcap3 and vcap4, and remove ocr_dis jumper. dspo design power supplies MC56F8323EVM.dsn 1.1 12 13 monday, may 12, 2003 b dsp standard products division 2100 east elliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 +3.3v +3.3v +3.3va +3.3v vcc +3.3va +5.0v +5.0v +5.0v +3.3va +vrefh +12v +5.0v +vrefh +5.0v +12v +3.3v +5.0v vddcore +3.3v_pll c10 0.1uf u12 mc33269dt-5.0 3 2 4 1 vin vout vout gnd l2 ferrite bead l6 ferrite bead + c45 47uf 10vdc + c43 470uf 16vdc + c44 47uf 10vdc l3 ferrite bead tp5 1 tp4 1 tp1 1 tp6 1 tp2 1 tp3 1 d2 fm4001 p3 1 3 2 -+ d1 3 1 4 2 c12 0.1uf + c47 47uf 10vdc u14 mc33269dt-3.3 3 2 4 1 vin vout vout gnd r13 270 led13 green led l5 ferrite bead l4 ferrite bead + c46 47uf 10vdc c11 0.1uf u15 reg113na-3/3k 1 5 4 2 3 vin vout nr gnd en + c48 10uf 6vdc c36 0.01uf jg11 1 2 r68 0 ohm u13 mc33269dt-3.3 3 2 4 1 vin vout vout gnd d4 fm4001 dnp d3 fm4001 dnp r67 0 ohm dnp tp7 1 tp9 1 tp11 1 tp8 1 tp10 1 r69 0 ohm j14 1 2 r75 0 ohm 56f8323evm schematics, rev. 2 freescale semiconductor appendix a-13 preliminary figure a-12. power supplies
a a b b c c d d e e 4 4 3 3 2 2 1 1 mc56f8323 a/d connector u8 pca82c250 max5251 74ac04 74ac00 max3245 74lcx244 74ac04 74hc244 u10 u9 u11 u6 u7 u3 j6 u1 u5 peripheral connector j1 memory connector j2 dspo design bypass capacitors MC56F8323EVM.dsn 1.1 13 13 friday, june 20, 2003 b dsp standard products division 2100 east elliot road tempe, arizona 85284 title document date: size designer: sheet of rev. number (480) 413-5090 fax: (480) 413-2510 +5.0v +3.3v +vref +3.3v +3.3va +3.3v +3.3v +3.3v +3.3v +3.3v +vsel +5.0v +3.3v +12v +vrefh +5.0v +3.3v +3.3v +vrefh c24 0.1uf c19 0.1uf c20 0.1uf c21 0.1uf c23 0.1uf c38 0.01uf c31 0.1uf c22 0.1uf c37 0.01uf c17 0.1uf c16 0.1uf c15 0.1uf c14 0.1uf c13 0.1uf c25 0.1uf c39 0.01uf c18 0.1uf c26 0.1uf c40 0.01uf c27 0.1uf c28 0.1uf c29 0.1uf c30 0.1uf c57 0.1uf c58 0.1uf c59 0.01uf MC56F8323EVM user manual, rev. 2 appendix a-14 freescale semiconductor preliminary figure a-13. bypass capacitors
56f8323evm bill of material, rev. 2 freescale semiconductor appendix b-1 preliminary appendix b 56f8323evm bill of material qty description ref. designators vendor part # integrated circuits 1 mc56f8323 u1 freescale semiconductor, mc56f8323vfb60 0 power-on reset u2 (optional) dallas semiconductor, ds1818 1 rs-232 transceiver u3 maxim, max3245eeai 0 spi 4-channel d/a u5 (optional) maxim, max5251beap 2 74ac04 u6, u7 on semiconductor, mc74ac04ad 1 can transceiver u8 philips semiconductor, pca82c250t 1 74hc244 u9 on semiconductor, mc74lhc44aadw 1 74lcx244 u10 on semiconductor, mc74lcx244adw 1 74ac00 u11 fairchild, 74ac00sc 1 +5.0v voltage regulator u12 on semiconductor, mc33269dt-5 2 +3.3v voltage regulator u13, u14 on semiconductor, mc33269dt-3.3 1 +3.0v voltage regulator u15 burr-brown, reg113na-3/3k resistors 13 270 ? r1?r13 smec, rc73l2a271ohmjt 1 1m ? r14 smec, rc73l2a105ohmjt 8 47k ? r15?r22 smec, rc73l2a473ohmjt 4 10k ? r23, r24, r25, r27 smec, rc73l2a103ohmjt 11 1k ? r26, r28?r30, r32, r34?r37, r74, r81 smec, rc73l2a103ohmjt
MC56F8323EVM user manual, rev. 2 appendix b-2 freescale semiconductor preliminary resistors (continued) 1 120 ? , 1/4w r38 yageo, cfr 120qbk 7 5.1k ? r41?r47 smec, rc73l2a512ohmjt 13 0 ? r51?r55, r68, r69, r75?r80 smec, rc73jp2a 2 51 ? r56, r57 smec, rc73l2a51ohmjt 0 5.1k ? r58 (optional) smec, rc73l2a512ohmjt 8 100 ? r59?r66 smec, rc73l2a101ohmjt 0 0 ? r67, r70?r73 (optional) smec, rc73jp2a 0 1k ? r82 (optional) smec, rc73l2a103ohmjt potentioneters 0 1k ? r48 (optional) bc/mepcopal, st4b102ct inductors 1 can bus filter l1 epcos, b82790-s0513-n201 5 1.0mh ferrite bead l2?l6 panasonic, exc-elsa35v leds 2 red led led1, led4 hewlett-packard, hsms-c650 5 yellow led led2, led5, led7, led9, led11 hewlett-packard, hsmy-c650 6 green led led3, led6, led8, led10, led12, led13 hewlett-packard, hsmg-c650 diode 1 +50v 1a bridge rect d1 diodes, df02s 1 s2b-fm401 d2 vishay, dl4001dict 0 s2b-fm401 d3 & d4 (optional) vishay, dl4001dict capacitors 4 2.2 f, +25v dc (low esr) c1?c4 taiyo yuden, celmk212bj225mg-t 29 0.1 f c5?c31, c57, c58 smec, mcce104k2nr-t1 4 1.0 f, +25v dc c32?c35 smec, mcce105k3nr-t1 qty description ref. designators vendor part #
56f8323evm bill of material, rev. 2 freescale semiconductor appendix b-3 preliminary capacitors (continued) 6 0.01 f c36?c40, c59 smec, mcce103k2nr-t1 1 0.001 f c41 smec, mcce102k2nr-t1 1 100pf c42 smec, mcce101k2nr-t1 1 470 f, +16v dc c43 elma, rv-16v471mh10r 4 47 f, +16v dc c44?c47 elma, rv2-16v470m-r 1 10 f, +10v dc c48 kemet, t494b106m010as 8 0.0022 f c49?c56 smec, mcce222k2nr-t1 jumpers 4 3 1 bergstick jg1, jg7, jg8, jg14 samtec, tsw-103-07-s-s 8 1 2 bergstick jg2, jg3, jg4, jg6, jg10, jg11, jg12, jg13 samtec, tsw-102-07-s-s 2 2 2 bergstick jg5, jg15 samtec, tsw-102-07-s-d 0 1 2 bergstick jg9 (optional) samtec, tsw-102-07-s-s test points 4 gnd test point tp1?tp3, tp10 keystone, 5001 (black) 1 gnda test point tp4 keystone, 5002 (white) 1 +3.3va test point tp5 keystone, 5004 (yellow) 2 +3.3v test point tp6, tp11 keystone, 5000 (red) 1 +5.0v & +12v test point tp7, tp8, tp9 keystone, 5003 (orange) 0 1 1 bergstick t15, t16 (optional) samtec, tsw-101-06-s-s crystals 1 8.00mhz crystal y1 cts, ats08asm-t connectors 1 db25m connector p1 amphenol, 617-c025p-aj121 1 de9s connector p2 amphenol, 617-c009s-aj120 1 2.1mm coax power connector p3 switchcraft, rapc-722 qty description ref. designators vendor part #
MC56F8323EVM user manual, rev. 2 appendix b-4 freescale semiconductor preliminary connectors (continued) 1 peripheral daughter card connector j1 hrs, fx6-100p-0.8sv2 1 memory bus daughter card connector j2 hrs, fx6-60p-0.8sv2 1 7x2 jtag header j3 samtec, tsw-107-07-s-d 0 4x2 header j4 (optional) samtec, tsw-104-07-s-d 5 5x2 header j6, j12, j13, j18, j19 samtec, tsw-105-07-s-d 2 7x2 header j5, j16 samtec, tsw-107-07-s-d 5 3x2 header j7, j8, j11, j15, j17, j21 samtec, tsw-103-07-s-d 2 2x2 header j9, j10 samtec, tsw-102-07-s-d 1 1x2 header j14 samtec, tsw-102-07-s-s switches 2 spst pushbutton s1?s2 panasonic, evq-pad05r transistors 1 2n2222a q1 zetex, fmmt2222act miscellaneous 13 shunt sh1?sh13 samtec, snt-100-bl-t 4 rubber feet rf1?rf4 3m, sj5018blkc qty description ref. designators vendor part #
index index, rev. 2 freescale semiconductor index - i preliminary numerics 1.2 amp power supply 2-12 4-channel 10-bit serial d/a 2-2 56f8300 peripheral user manual 2-3 56f8323 preface-ix 56f8323 technical data sheet 2-3 8.00mhz crystal oscillator 2-1 a a/d preface-ix adc preface-ix analog-to-digital a/d preface-ix analog-to-digital converter adc preface-ix c can preface-ix bus termination 2-1 bypass 2-1 interface 2-1 can in automation cia preface-ix can physical layer peripheral 2-2 cia preface-ix clear to send cts preface-ix controller area network can preface-ix cts preface-ix d d/a preface-ix daughter card expansion interface 2-1 debugging 2-6 digital-to-analog d/a preface-ix dsp56800e reference manual 2-3 e enhanced on-chip emulation eonce preface-ix eonce preface-ix evaluation module evm preface-ix evm preface-ix external oscillator frequency input 2-1 f flexcan preface-ix flexcan interface module flexcan preface-ix g general purpose input and output gpio preface-ix gpio preface-ix h host parallel interface connector 2-8 host target interface 2-8 i ic preface-ix integrated circuit ic preface-ix j joint test action group jtag preface-ix jtag preface-ix , 2-1 jtag/enhanced once (eonce) 1-1 jumper group 1-4 jg1 1-4 jg10 1-4 jg11 1-4 jg12 1-4 jg13 1-4 jg14 1-4 jg15 1-4 jg2 1-4 jg3 1-4 jg4 1-4 jg5 1-4 jg6 1-4 jg7 1-4 jg8 1-4 jg9 1-4
MC56F8323EVM user manual, rev. 2 index-ii freescale semiconductor preliminary l led preface-ix light emitting diode led preface-ix low-profile quad flat package lqfp preface-ix lqfp preface-ix m mpio preface-ix multi purpose input and output mpio preface-ix o on-board power regulation 2-2 once preface-x on-chip emulation once preface-x p parallel jtag host target interface 2-1 pcb preface-x peripheral port signals 2-14 phase locked loop pll preface-x pll preface-x printed circuit board pcb preface-x pulse width modulation pwm preface-x pwm preface-x pwma-compatible peripheral 2-2 q quaddec preface-x quadrature decoder interface port 2-26 quaddec preface-x r r/c preface-x real-time debugging 2-6 request to send rts preface-x resistor/capacitor network r/c preface-x rs-232 2-1 level converter 2-4 schematic diagram 2-4 rts preface-x s sci preface-x sci/mpio-compatible peripheral 2-2 serial communications interface sci preface-x serial peripheral interface spi preface-x spi preface-x spi/mpio-compatible peripheral 2-2 sram preface-x static random access memory sram preface-x t timer-compatible peripheral 2-2 u uart preface-x universal asynchronous receiver/transmitter uart preface-x w wait state ws preface-x ws preface-x

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